Skip to content

GT Themes: 2024

Note

For questions, email khanh@u-aizu.ac.jp. The supervisor's office is 204-I, Research Quadrangles.

Mentoring

See student project examples from our group.

From joining to graduation

GT flow GT flow

Laboratory guidelines

  1. Our group consists of 2 Master students and 7 undergraduate students (see Group Members).
  2. Group meeting: twice a month (1st and 3rd week).
  3. Face-to-face meeting with each student: twice a month (2nd and 4th week). This meeting can be flexible depending on the progress.
  4. Lab meeting: twice a week.
  5. From the fourth year, you must present progress reports.
  6. For excellent students, paper submissions and traveling for conferences (in Japan or abroad) are strongly recommended.
  7. Further reading:
    • How we work: link
    • What can you learn: link

What you can learn from a GT project

  1. We adapt schedules and supervision to students' experience and working styles. The supervisor is available for discussion, and students can ask for help in a friendly lab environment.
  2. You can practise English with both Japanese and international students (see Group Members)!
  3. Build and test working prototypes. (see some sample projects by students here)!
  4. Practise making slides, presenting your work, answering questions, and writing reports.
  5. For excellent students, you will learn how to write a paper, travel abroad, and present. See this paper for an example of a B4 student's paper.

Topics

Power-Efficient Spiking Neural Network

This project aims to research and implement an adaptive, low-power spiking neural network system in hardware (NASH) based on our earlier-developed OASIS communication network. NASH implements the following features (1) an efficient adaptive configuration method that enables reconfiguration of different SNN parameters (spike weights, routing, hidden layers, topology, etc.), (2) a mixture of different deep NN topologies, (3) an efficient fault-tolerant multicast spike routing algorithm, (4) Efficient on-chip learning mechanism. The project includes FPGA and VLSI implementations to demonstrate NASH performance.

Students can work on software (Python), or hardware (VLSI/FPGA) or both.

Demonstration of previous design

  1. See this slide for the demo: 2023_Demo_FPGA.pdf.
  2. Video of the SNN SoC on FPGA:

Reading materials

Low-power Generative Adversarial Network

A low-power Generative Adversarial Network (GAN) is an energy-efficient version of a traditional GAN, optimized for environments with limited computational resources. By using techniques like model compression and approximate computing, it reduces energy consumption, enabling real-time data generation on low-power devices like smartphones, IoT systems, and neuromorphic hardware.

You will build a baseline GAN in PyTorch or Verilog HDL, then reduce its power consumption using our existing techniques, such as approximate computing, approximate memory, or data compression.

Students can work on software (Python), or hardware (VLSI/FPGA) or both.

"Green" AI Computing (You can pick your AI application)

You can propose an AI application and investigate it using our power-efficient computing techniques ("Green" AI). We will discuss your idea and support its development.

In this project, you will deploy AI model in combination with our power efficient techniques:

当研究室の省電力技術（「グリーン」AI）を使い、独自のAIアプリケーションを提案できるテーマです。取り組みたいアプリケーションがあれば、ご相談ください。研究の進め方を一緒に考えます。

このプロジェクトでは、当研究室の省電力技術と組み合わせて AI モデルを展開します。

Some notes

  • You can propose your own AI application. 独自のAIアプリケーションを提案できます。If you want to start your company with AI computing, we welcome and support you! AIコンピューティングで会社を立ち上げたい方は、ぜひご応募ください。
  • We can help file a patent for your technology. See our previous patents: https://u-aizu.ac.jp/~khanh/patent. ご希望であれば、あなたの技術で特許を申請することもできます。以前の特許をご覧ください: https://u-aizu.ac.jp/~khanh/patent.